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1 LTC1864L/ltc1865l 18645lf applicatio s u features descriptio u typical applicatio u m power, 3v, 16-bit, 150ksps 1- and 2-channel adcs in msop single 3v supply, 150ksps, 16-bit sampling adc supply current vs sampling frequency the ltc ? 1864l/ltc1865l are 16-bit a/d converters that are offered in msop and so-8 packages and operate on a single 3v supply. at 150ksps, the supply current is only 450 m a. the supply current drops at lower speeds because the LTC1864L/ltc1865l automatically power down between conversions. these 16-bit switched capacitor successive approximation adcs include sample-and-holds. the LTC1864L has a differential analog input with an external reference pin. the ltc1865l offers a software- selectable 2-channel mux and an external reference pin on the msop version. the 3-wire, serial i/o, small msop or so-8 package and extremely high sample rate-to-power ratio make these adcs ideal choices for compact, low power, high speed systems. these adcs can be used in ratiometric applications or with external references. the high impedance analog inputs and the ability to operate with reduced spans down to 1v full scale allow direct connection to signal sources in many applications, eliminating the need for external gain stages. n 16-bit 150ksps adcs in msop package n single 3v supply n low supply current: 450 m a (typ) n auto shutdown reduces supply current to 10 m a at 1ksps n true differential inputs n 1-channel (LTC1864L) or 2-channel (ltc1865l) versions n spi/microwire tm compatible serial i/o n 16-bit upgrade to 12-bit ltc1285/ltc1288 n pin compatible with 12-bit ltc1860l/ltc1861l n no minimum data transfer rate , ltc and lt are registered trademarks of linear technology corporation. n high speed data acquisition n portable or compact instrumentation n low power battery-operated instrumentation n isolated and/or remote data acquisition 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1864L 1864 ta01 analog input 0v to 3v 3v 1 m f serial data link to asic, pld, mpu, dsp or shift registers microwire is a trademark of national semiconductor corporation. sampling frequency (khz) 0.1 supply current ( a) 1 10 100 1000 0.01 1 10 1000 1864l/65l ta02 0.1 100 conv low = 2 s t a = 25 c v cc = 2.7v ( datasheet : )
2 LTC1864L/ltc1865l 18645lf operating temperature range LTC1864Lc/ltc1865lc/ LTC1864Lac/ltc1865lac .................... 0 c to 70 c LTC1864Li/ltc1865li/ LTC1864Lai/ltc1865lai ................. C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c supply voltage (v cc ) ................................................. 7v ground voltage difference agnd, dgnd ltc1865l msop package ......... 0.3v analog input ............... (gnd C 0.3v) to (v cc + 0.3v) digital input ................................ (gnd C 0.3v) to 7v digital output .............. (gnd C 0.3v) to (v cc + 0.3v) power dissipation .............................................. 400mw (notes 1, 2) order part number ms8 part marking ms part marking ltj4 ltj5 ltc1865lcms ltc1865lims ltc1865lacms ltc1865laims order part number LTC1864Lcms8 LTC1864Lims8 LTC1864Lacms8 LTC1864Laims8 ltc7 ltc8 t jmax = 150 c, q ja = 210 c/w t jmax = 150 c, q ja = 210 c/w 1 2 3 4 v ref in + in? gnd 8 7 6 5 v cc sck sdo conv top view ms8 package 8-lead plastic msop absolute axi u rati gs w ww u package/order i for atio uu w ltc9 ltd1 order part number s8 part marking s8 part marking 1864l 1864li LTC1864Lcs8 LTC1864Lis8 LTC1864Lacs8 LTC1864Lais8 order part number t jmax = 150 c, q ja = 175 c/w 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v ref in + in gnd v cc sck sdo conv 1864la 864lai ltj6 ltj7 1865l 1865li ltc1865lcs8 ltc1865lis8 ltc1865lacs8 ltc1865lais8 1865la 865lai 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so conv ch0 ch1 gnd v cc sck sdo sdi t jmax = 150 c, q ja = 175 c/w 1 2 3 4 5 conv ch0 ch1 agnd dgnd 10 9 8 7 6 v ref v cc sck sdo sdi top view ms package 10-lead plastic msop l LTC1864L/ltc1865l LTC1864La/ltc1865la parameter conditions min typ max min typ max units resolution l 16 16 bits no missing codes resolution l 14 15 bits inl (note 3) l 8 6 lsb transition noise 2 2 lsb rms gain error l 20 20 mv co verter a d ultiplexer characteristics u wu consult ltc marketing for parts specified with wider operating temperature ranges. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 2.7v, v ref = 2.5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted.
3 LTC1864L/ltc1865l 18645lf LTC1864L/ltc1865l symbol parameter conditions min typ max units snr signal-to-noise ratio 82 db s/(n + d) signal-to-noise plus distortion ratio 1khz input signal 82 db thd total hamonic distortion up to 5th harmonic 1khz input signal 92 db full power bandwidth 10 mhz full linear bandwidth s/(n + d) 3 75db 20 khz parameter conditions min typ max min typ max units offset error l 2 5 2 5mv input differential voltage v in = in + C in C l 0v ref 0v ref v range absolute input range in + input C 0.05 v cc + 0.05 C 0.05 v cc + 0.05 v in C input C 0.05 v cc /2 C 0.05 v cc /2 v v ref input range LTC1864L so-8 and msop, ltc1865l msop 1 v cc 1v cc v analog input leakage current (note 4) l 1 1 m a c in input capacitance in sample mode 12 12 pf during conversion 5 5 pf dy a ic accuracy u w digital a d dc electrical characteristics u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 2.7v, v ref = 2.5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. co verter a d ultiplexer characteristics u wu t a = 25 c. v cc = 3v, v ref = 3v, f sample = 150khz, unless otherwise noted. LTC1864L/ltc1865l symbol parameter condition min typ max units v ih high level input voltage v cc = 3.3v l 1.9 v v il low level input voltage v cc = 2.7v l 0.45 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C 2.5 m a v oh high level output voltage v cc = 2.7v, i o = 10 m a l 2.3 2.6 v v cc = 2.7v, i o = 360 m a l 2.1 2.45 v v ol low level output voltage v cc = 2.7v, i o = 400 m a l 0.3 v i oz hi-z output leakage conv = v cc l 3 m a i source output source current v out = 0v C 6.5 ma i sink output sink current v out = v cc 6.5 ma i ref reference current (LTC1864L so-8 and conv = v cc l 0.001 3 m a msop, ltc1865l msop) f smpl = f smpl(max) l 0.01 0.1 ma i cc supply current conv = v cc after conversion l 0.5 10 m a f smpl = f smpl(max) l 0.45 1.0 ma p d power dissipation f smpl = f smpl(max) 1.22 mw LTC1864L/ltc1865l LTC1864La/ltc1865la the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 2.7v, v ref = 2.5v, unless otherwise noted.
4 LTC1864L/ltc1865l 18645lf LTC1864L/ltc1865l symbol parameter conditions min typ max units v cc supply voltage 2.7 3.6 v f sck clock frequency l dc 8 mhz t cyc total cycle time 16 ? sck + t conv m s t smpl analog input sampling time (note 5) LTC1864L 16 sck ltc1865l 14 sck t suconv setup time conv before first sck - 60 ns (see figure 1) t hdi hold time sdi after sck - ltc1865l 30 ns t sudi setup time sdi stable before sck - ltc1865l 30 ns t whclk sck high time f sck = f sck(max) 45% 1/f sck t wlclk sck low time f sck = f sck(max) 45% 1/f sck t whconv conv high time between data t conv m s transfer cycles t wlconv conv low time during data transfer 16 sck t hconv hold time conv low after last sck - 26 ns LTC1864L/ltc1865l symbol parameter conditions min typ max units t conv conversion time (see figure 1) l 3.7 4.66 m s f smpl(max) maximum sampling frequency l 150 khz t ddo delay time, sck to sdo data valid c load = 20pf 45 55 ns l 60 ns t dis delay time, conv - to sdo hi-z l 55 120 ns t en delay time, conv to sdo enabled c load = 20pf l 35 120 ns t hdo time output data remains c load = 20pf l 515 ns valid after sck t r sdo rise time c load = 20pf 25 ns t f sdo fall time c load = 20pf 12 ns reco e ded operati g co ditio s u u u uw w ti i g characteristics u w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 2.7v, v ref = 2.5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: channel leakage current is measured while the part is in sample mode. note 5: assumes f sck = f sck(max) in the case of the LTC1864L sck does not have to be clocked during this time if the sdo data word is not desired. in the case of the ltc1865l a minimum of 2 clocks are required on the sck input after conv falls to configure the mux during this time.
5 LTC1864L/ltc1865l 18645lf typical perfor a ce characteristics uw supply current vs sampling frequency supply current vs temperature sleep current vs temperature reference current vs sampling rate reference current vs temperature reference current vs reference voltage typical inl curve typical dnl curve analog input leakage current vs temperature sampling frequency (khz) 0.1 supply current ( a) 1 10 100 1000 0.01 1 10 1000 1864l/65l g01 1864l/65l g02 1864l/65l g03 0.1 100 conv low = 2 s t a = 25 c v cc = 2.7v temperature ( c) ?0 supply current ( a) 600 500 400 300 200 100 0 25 75 ?5 0 50 100 125 f s = 150khz v cc = 2.7v v ref = 2.5v temperature ( c) ?0 shutdown current ( a) 20 15 10 5 0 25 75 ?5 0 50 100 125 f s = 150khz v cc = 2.7v v ref = 2.5v sampling frequency (khz) 0 reference current ( a) 25 50 75 100 1864l/65l g04 125 10 9 8 7 6 5 4 3 2 1 0 150 conv low = 2 s t a = 25 c v cc = 2.7v v ref = 2.5v temperature ( c) ?0 reference current ( a) 25 20 15 10 5 0 25 75 1864l/65l g05 ?5 0 50 100 125 f s = 150khz v cc = 2.7v v ref = 2.5v reference voltage (v) 0 reference current ( a) 0.5 1.0 2.0 1.5 3.0 2.5 1864l/65l g06 3.5 25 20 15 10 5 0 4.0 f s = 150khz t a = 25 c v cc = 3.6v temperature ( c) ?0 analog input leakage (na) 100 75 50 25 0 25 75 1864l/65l g09 ?5 0 50 100 125 conv = 0v v cc = 2.7v v ref = 2.5v code 0 inl error (lsbs) 0 2 65536 1865 g02 ? ? 16384 32768 49152 4 v cc = 2.7v v ref = 2.5v f s = 150khz code 0 dnl error (lsbs) 0 1 65536 1865 g03 ? ? 16384 32768 49152 2 v cc = 2.7v v ref = 2.5v f s = 150khz
6 LTC1864L/ltc1865l 18645lf reference voltage (v) 0 change in offset (lsb) 4 1864l/65l g10 1 2 3 20 15 10 5 0 ? ?0 ?5 ?0 f s = 150khz t a = 25 c v cc = 3.6v reference voltage (v) 0 ghange in gain error (lsb) 4 1864l/65l g12 1 2 3 f s = 150khz t a = 25 c v cc = 3.6v temperature ( c) ?0 25 75 1864l/65l g11 ?5 0 50 100 125 change in offset (lsb) 5 4 3 2 1 0 ? ? ? ? ? 5 4 3 2 1 0 ? ? ? ? ? v cc = 2.7v v ref = 2.5v 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 temperature ( c) ?0 25 75 1864l/65l g13 1864l/65l g14 ?5 0 50 100 125 change in gain error (lsb) 5 4 3 2 1 0 ? ? ? ? ? thd (db) 1864l/65l g15 input frequency (khz) 1 sinad (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1864l/65l g16 input frequency (khz) 1 10 100 1864l/65l g17 sfdr (db) 100 90 80 70 60 50 40 30 20 10 0 input frequency (khz) 1 10 100 1864l/65l g18 30 31 33 35 37 39 41 43 32 34 36 38 40 42 44 frequency 1200 1000 800 600 400 200 0 code v cc = 2.7v v ref = 2.5v f s = 125khz t a = 25 c v cc = 3v v in = 0db v ref = 3v f s = 125khz t a = 25 c v cc = 3v v in = 0db v ref = 3v f s = 125khz t a = 25 c v cc = 3v v in = 0db v ref = 3v snr sinad 0 7 52 45 20 00 169 407 1040 648 152 291 576 689 input frequency (khz) 0 amplitude (db) 60 5101520253540505565 30 45 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 f s = 125khz t a = 25 c v cc = 3v v in = 0.946045khz v ref = 3v typical perfor a ce characteristics uw sinad vs input frequency thd vs input frequency sfdr vs input frequency change in offset vs reference voltage change in offset vs temperature change in gain error vs reference voltage change in gain error vs temperature histogram of 4096 conversions of a dc input voltage 4096 point fft nonaveraged
7 LTC1864L/ltc1865l 18645lf v ref (pin 1): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. in + , in C (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. conv (pin 5): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this pin. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. uu u pi fu ctio s ltc1865l (msop package) conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to agnd. agnd (pin 4): analog ground. agnd should be tied directly to an analog ground plane. dgnd (pin 5): digital ground. dgnd should be tied directly to an analog ground plane. sdi (pin 6): digital data input. the a/d configuration word is shifted into this input. conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. ltc1865l (so-8 package) sdo (pin 7): digital data output. the a/d conversion result is shifted out of this output. sck (pin 8): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 9): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref (pin 10): reference input. the reference input de- fines the span of the a/d converter and must be kept free of noise with respect to agnd. sdi (pin 5): digital data input. the a/d configuration word is shifted into this input. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this output. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref is tied internally to this pin. LTC1864L
8 LTC1864L/ltc1865l 18645lf load circuit for t ddo , t r , t f , t dis and t en voltage waveforms for sdo rise and fall times, t r , t f voltage waveforms for sdo delay times, t ddo and t hdo voltage waveforms for t en sdo 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1864 tc01 sck sdo v il t ddo t hdo v oh v ol 1864 tc02 1864 tc03 conv sdo t en sdo t r t f 1864 tc04 v oh v ol test circuits voltage waveforms for t dis sdo waveform 1 (see note 1) v ih t dis 90% 10% sdo waveform 2 (see note 2) conv note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 1864 tc05 fu n ctio n al block diagra uu w 1864/65 bd 16-bit sampling adc bias and shutdown convert clk serial port 16 bits in + (ch0) in (ch1) v cc v ref sdo gnd conv (sdi) sck pin names in parentheses refer to ltc1865l data out data in +
9 LTC1864L/ltc1865l 18645lf LTC1864L operation operating sequence the LTC1864L conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conver- sion is finished. if conv is left high after this time, the LTC1864L goes into sleep mode drawing only leakage current. on the falling edge of conv, the LTC1864L goes into sample mode and sdo is enabled. sck synchronizes the data transfer with each bit being transmitted from sdo on the falling sck edge. the receiving system should capture the data from sdo on the rising edge of sck. after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefinitely. see figure 1. analog inputs the LTC1864L has a unipolar differential analog input. the converter will measure the voltage between the in + and in C inputs. a zero code will occur when in + minus in C equals zero. full scale occurs when in + minus in C equals v ref minus 1lsb. see figure 2. both the in + and in C inputs are sampled at the same time, so common mode noise on the inputs is rejected by the adc. if in C is grounded and v ref is tied to v cc , a rail-to-rail input span will result on in + as shown in figure 3. reference input the voltage on the reference input of the LTC1864L defines the full-scale range of the a/d converter. the LTC1864L can operate with reference voltages from v cc to 1v. conv t conv sck sdo 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b15 b14 b12 b10 b8 b6 b4 b2 b0* hi-z 1854 f01 hi-z b13 b11 b9 b7 b5 b3 b1 sleep mode t smpl *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely don't care 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1864L 1864 f03 v in = 0v to v cc v cc 1 m f serial data link to asic, pld, mpu, dsp or shift registers figure 1. LTC1864L operating sequence figure 3. LTC1864L with rail-to-rail input span figure 2. LTC1864L transfer curve 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in * *v in = in + ?in 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1864 f02 applicatio s i for atio wu uu
10 LTC1864L/ltc1865l 18645lf ltc1865l operation operating sequence the ltc1865l conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conver- sion is finished. if conv is left high after this time, the ltc1865l goes into sleep mode drawing only leakage current. the ltc1865ls 2-bit data word is clocked into the sdi input on the rising edge of sck after conv goes low. additional inputs on the sdi pin are then ignored until the next conv cycle. the shift clock (sck) synchronizes the data transfer with each bit being transmitted on the falling sck edge and captured on the rising sck edge in both transmitting and receiving systems. the data is transmitted and received simultaneously (full duplex). after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefi- nitely. see figure 4. analog inputs the two bits of the input word (sdi) assign the mux configuration for the next requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of table 1. in conv sdi sck 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 sdo b15 b14 b12 b10 b8 b6 b4 b2 b0* hi-z b13 b11 b9 b7 b5 b3 b1 s/d o/s don? care don? care t conv 1864 f04 sleep mode *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely hi-z t smpl don't care figure 4. ltc1865l operating sequence applicatio s i for atio wu uu mux address table 1. multiplexer channel selection sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + + gnd 1864 tbl1 single-ended mux mode differential mux mode single-ended mode, all input channels are measured with respect to gnd. a zero code will occur when the + input minus the C input equals zero. full scale occurs when the + input minus the C input equals v ref minus 1lsb. see figure 5. both the + and C inputs are sampled at the same time so common mode noise is rejected. the input span in the so-8 package is fixed at v ref = v cc . if the C input in differential mode is grounded, a rail-to-rail input span will result on the + input. reference input the reference input of the ltc1865l so-8 package is internally tied to v cc . the span of the a/d converter is therefore equal to v cc . the voltage on the reference input of the ltc1865l msop package defines the span of the a/d converter. the ltc1865l msop package can operate with reference voltages from 1v to v cc .
11 LTC1864L/ltc1865l 18645lf general analog considerations grounding the LTC1864L/ltc1865l should be used with an analog ground plane and single point grounding techniques. do not use wire wrapping techniques to breadboard and evaluate the device. to achieve the optimum performance, use a printed circuit board. the ground pins (agnd and dgnd for the ltc1865l msop package and gnd for the LTC1864L and ltc1865l so-8 package) should be tied directly to the analog ground plane with minimum lead length. bypassing for good performance, the v cc and v ref pins must be free of noise and ripple. any changes in the v cc /v ref voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. bypass the v cc and v ref pins directly to the analog ground plane with a minimum of 1 m f tantalum. keep the bypass capacitor leads as short as possible. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the LTC1864L/ ltc1865l have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem if source resistances are less than 200 w or high speed op amps are used (e.g., the lt ? 1211, lt1469, lt1807, lt1810, lt1630, lt1226 or lt1215). but if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conver- sion begins. applicatio s i for atio wu uu 0v 1lsb v cc ?2lsb v cc ?1lsb v cc v in * *v in = (selected ??channel) (selected ?channel) refer to table 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1864 f05 figure 5. ltc1865l transfer curve
12 LTC1864L/ltc1865l 18645lf applicatio s i for atio wu uu LTC1864L evaluation circuit schematic u12b 74ac109 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 jp8 246 135 jp9 246 135 2 3 4 1 5 6 7 8 10 9 8 3.3v dig 3.3v dig 3.3v dig 3.3v dig 3.3v dig 15v ?5v 3.3v dig 3.3v dig 3.3v an 3.3v dig 3.3v dig 3.3v dig c16 0.1 f c23 0.1 f c5 0.1 f c6 0.1 f c24 0.1 f c18 0.1 f c17 0.1 f 3.3v dig 3.3v dig 3.3v dig c13 0.1 f c12 10 f 6.3v 1206 c14 0.1 f u12a 74ac109 u10 ltc1799 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u6 74hc163ad j k clk clr pre q q gnd v cc 1 2 3 5 4 v + gnd set div 14 13 12 15 11 j k clk clr pre q q gnd v cc 16 16 u9b 74ac00 u9a 74ac00 u13b 74ac32 reset clk p0 p1 p2 p3 enp gnd v cc rco q0 q1 q2 q3 ent lo u7 74hc163ad r10 10k 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 j4 3201s40g1 qb qc qd qe qf qg qh gnd v cc qa a oenb lclk sclk reset sqh rn1 330 qb qc qd qe qf qg qh gnd v cc qa a oenb lclk sclk reset sqh r9 51 c8 470pf 1205 c9 100pf 1206 c7 100pf 1206 c20 0.1 f c1 0.1 f c4 0.1 f c21 47pf c22 47pf c10 0.1 f 3.3v dig c15 0.1 f 3.3v dig c19 0.1 f c2 1 f 10v 0805 c3 10 f 6.3v 1206 ?n jp3 buf jp2 jp1 +in r1 100 1206 r3 2 r2 100 v in v out gnd u1 lt1460dcs8-2.5 v in v out gnd r4 2 15v 15v in + in + agnd in in v ref +in ?n gnd v cc sclk d out conv u8a 74ac14 u8b 74ac14 u8e 74ac14 u8d 74ac14 u8f 74ac14 out 15v 3.3v an u4 74hc595adt u5 74hc595adt u9c 74ac00 u9d 74ac00 u13a 74ac32 u13d 74ac32 u13c 74ac32 analog ground plane clk jp6 clk jp7 extck jp4 conv j1 j2 e1 e8 e9 u2 opt u3 LTC1864Laims8 1 2 3 4 8 7 6 5 r6 402 1% r5 402 1% 1 2 3 4 8 7 6 5 2 3 3 3 3 1 2 2 1 6 7 2 1 2 3 3 3 2 1 2 1 4 4 6 1 2 3 conv dgnd dgnd dout clkout clkin enable data u8c 74ac14 e2 e3 e7 e6 e4 e5 j3 notes: unless otherwise specified install shunts on jp1, jp3-jp7 pin 1 and pin2; on jp8 and jp9 pin 2 and pin 4, pin 3 and pin 5. 1864/65 ai1 r7 20k lt1121-3.3 ckin ckin ext int ext int r8 1m p0 p0 p1 p1 p2 p2 p3 p3 1 in + in buf on off gnd en jp5 3 2 1 gnd ext 56 32 56 32 5 6 3 2
13 LTC1864L/ltc1865l 18645lf applicatio s i for atio wu uu component side silk screen for LTC1864L evaluation circuit component side showing traces (note wider traces on analog side) bottom side showing traces (note almost no analog traces on board bottom) ground layer with separate analog and digital grounds supply layer with 5v digital supply and analog ground repeated
14 LTC1864L/ltc1865l 18645lf ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 0802 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.15 (1.93 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc u package descriptio
15 LTC1864L/ltc1865l 18645lf u package descriptio s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) msop (ms) 0802 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.13 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.15 (1.93 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc .016 ?.050 (0.406 ?1.270) .010 ?.020 (0.254 ?0.508) 45 0 ?8 typ .008 ?.010 (0.203 ?0.254) so8 0303 .053 ?.069 (1.346 ?1.752) .014 ?.019 (0.355 ?0.483) typ .004 ?.010 (0.101 ?0.254) .050 (1.270) bsc 1 2 3 4 .150 ?.157 (3.810 ?3.988) note 3 8 7 6 5 .189 ?.197 (4.801 ?5.004) note 3 .228 ?.244 (5.791 ?6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm)
16 LTC1864L/ltc1865l 18645lf lt/tp 0303 2k ? printed in usa related parts ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com u typical applicatio tiny 2-chip data acquisition system + ltc6910-1 0.1 f 1 f 1 f 3v 3v agnd 3 8 4 1 2 7 6 5 v in gain control adc control 499 270pf v ref in + in gnd v cc sck sdo conv LTC1864L ltc6910-1 (in tsot-23 package) compactly adds 40db of input gain range to the LTC1864L (in msop 8-pin package). single 3v supply 1864l/65l ta03 part number sample rate power dissipation description 12-bit serial i/o adcs ltc1860l/ltc1861l 150ksps 1.22mw pin compatible with LTC1864L/ltc1865l ltc1860/ltc1861 250ksps 4.25mw pin compatible with ltc1864/ltc1865 14-bit serial i/o adcs ltc1417 400ksps 20mw 16-pin ssop, unipolar or bipolar, reference, 5v or 5v ltc1418 200ksps 15mw serial/parallel i/o, internal reference, 5v or 5v 16-bit serial i/o adcs ltc1609 200ksps 65mw configurable bipolar or unipolar input ranges, 5v ltc1864/ltc1865 250ksps 4.25mw msop, so-8, 1- and 2-channel, 5v supply references lt1460 micropower precision series reference bandgap, 130 m a supply current, 10ppm/ c, available in sot-23 lt1790 micropower low dropout reference 60 m a supply current, 10ppm/ c, sot-23 op amps lt1468/lt1469 single/dual 90mhz, 16-bit accurate op amps 22v/ m s slew rate, 75 m v/125 m v offset lt1806/lt1807 single/dual 325mhz low noise op amps 140v/ m s slew rate, 3.5nv/ ? hz noise, C 80dbc distortion lt1809/lt1810 single/dual 180mhz low distortion op amps 350v/ m s slew rate, C 90dbc distortion at 5mhz

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